verilog 随机数生成module test;reg [31:0] a,b,c,d;initialbegina = $random % 100; a[31] = 0;b = $random % 100; b[31] = 0;c = $random % 100; c[31] = 0;d = $random % 100; d[31] = 0;endinitialbegin#10 $display("%d,%d,%d,%d",a,b,c,d);#1000 $finish;end
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![verilog 随机数生成module test;reg [31:0] a,b,c,d;initialbegina = $random % 100; a[31] = 0;b = $random % 100; b[31] = 0;c = $random % 100; c[31] = 0;d = $random % 100; d[31] = 0;endinitialbegin#10 $display(](/uploads/image/z/6801798-30-8.jpg?t=verilog+%E9%9A%8F%E6%9C%BA%E6%95%B0%E7%94%9F%E6%88%90module+test%3Breg+%5B31%3A0%5D+a%2Cb%2Cc%2Cd%3Binitialbegina+%3D+%24random+%25+100%3B+a%5B31%5D+%3D+0%3Bb+%3D+%24random+%25+100%3B+b%5B31%5D+%3D+0%3Bc+%3D+%24random+%25+100%3B+c%5B31%5D+%3D+0%3Bd+%3D+%24random+%25+100%3B+d%5B31%5D+%3D+0%3Bendinitialbegin%2310+%24display%28%22%25d%2C%25d%2C%25d%2C%25d%22%2Ca%2Cb%2Cc%2Cd%29%3B%231000+%24finish%3Bend)
verilog 随机数生成module test;reg [31:0] a,b,c,d;initialbegina = $random % 100; a[31] = 0;b = $random % 100; b[31] = 0;c = $random % 100; c[31] = 0;d = $random % 100; d[31] = 0;endinitialbegin#10 $display("%d,%d,%d,%d",a,b,c,d);#1000 $finish;end
verilog 随机数生成
module test;
reg [31:0] a,b,c,d;
initial
begin
a = $random % 100; a[31] = 0;
b = $random % 100; b[31] = 0;
c = $random % 100; c[31] = 0;
d = $random % 100; d[31] = 0;
end
initial
begin
#10 $display("%d,%d,%d,%d",a,b,c,d);
#1000 $finish;
end
endmodule
这段代码在仿真时输出为
48,2147483549,2147483609,2147483639
为什么只有a是正确的?
verilog 随机数生成module test;reg [31:0] a,b,c,d;initialbegina = $random % 100; a[31] = 0;b = $random % 100; b[31] = 0;c = $random % 100; c[31] = 0;d = $random % 100; d[31] = 0;endinitialbegin#10 $display("%d,%d,%d,%d",a,b,c,d);#1000 $finish;end
{$random}%100.试试,random能生成负数.
若是-69,则-69%100=-69,补码的话看上去就会是一个很大的数.即便后来高位置零,其他位还是保留补码时的值,所以很大.